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Design and Hardware Chip Implementation of Wireless Network Topology for Smart Grid

Radius: Journal of Science and Technology

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Volume 2, Issue 1,  Article Number: 251001 (2025) 

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Payal Rani1,* | Lalit Kumar1  

1Research Scholar, Department of Electrical Engineering, School of Engineering & Technology, Shri Venkateshwara University, Gajraula, U.P (India)

*Corresponding Author: payalrani105@gmail.com

Received: 24 December 2024 | Revised: 04 January 2025

Accepted: 06 January 2025 | Published Online: 08 January 2025

DOI: https://doi.org/10.5281/zenodo.15008478

© 2025 The Authors, under a Creative Commons license, Published by Scholarly Publication

Abstract

This study mainly examines the establishment of wireless networks using hardware chips that stand a chance of improving the communication of smart grid by providing high reliability, low latency as well as data confidentiality. In the suggested setup, a hierarchical architecture together with central gateway, cluster heads and sensor nodes, is exploited to allow data aggregation and thus reduce transmission overhead. Among IoT devices, wireless technologies like Zigbee and LoRa are used to enhance communication quality, thanks to the fault tolerant technique that makes the system more reliable. By studying the theoretical groundwork and the necessary hardware needed in the smart grid communication, the research is intended to identify the most significant obstacles that make current energy transfer networks relatively ineffective.

Keywords

Embedded System Design, Energy Efficiency, FPGA, Low-Power Wireless Protocols, Microcontroller Integration, Optimization of Network Topologies, Smart Grid Communication, WSNs

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Cite This Article

P. Rani and L. Kumar, “Design and Hardware Chip Implementation of Wireless Network Topology for Smart Grid,” Radius: Journal of Science and Technology 2(1) (2025) 251001. https://doi.org/10.5281/zenodo.15008478

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